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Altera - EPF8282ALC84-4.pdf
   ®  Altera Corporation 1 FLEX 8000 Programmable LogicDevice Family January 2003, ver. 11.1Data Sheet DS-F8000-11.1 F  L  E  X   8   0   0   0   3 1 Features...  ■ Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see Table1)–2,500 to 16,000 usable gates–282 to 1,500 registers ■ System-level features–In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller–Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 5.0-V operation–Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices–MultiVolt TM  I/O interface enabling device core to run at 5.0V, while I/O pins are compatible with 5.0-V and 3.3-V logic levels–Low power consumption (typical specification is 0.5 mA or less in standby mode) ■ Flexible interconnect–FastTrack ®  Interconnect continuous routing structure for fast, predictable interconnect delays–Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions)–Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions)–Tri-state emulation that implements internal tri-state nets ■ Powerful I/O pins ■ Programmable output slew-rate control reduces switching noise Table 1.FLEX8000 Device Features  Feature EPF8282AEPF8282AVEPF8452A EPF8636A EPF8820A EPF81188A EPF81500A Usable gates 2,5004,0006,0008,00012,00016,000Flipflops2824526368201,1881,500Logic array blocks (LABs)26426384126162Logic elements (LEs)2083365046721,0081,296Maximum user I/O pins78120136152184208  2Altera CorporationFLEX 8000 Programmable Logic Device Family Data Sheet ...and More Features ■ Peripheral register for fast setup and clock-to-output delay ■ Fabricated on an advanced SRAM process ■ Available in a variety of packages with 84 to 304 pins (see Table2) ■ Software design support and automatic place-and-route provided by the Altera ®  MAX+PLUS ®  II development system for Windows-based PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations ■ Additional design entry and simulation support provided by EDIF 200 and 300 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and Veribest  Note: (1)FLEX8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages. General Description Altera’s Flexible Logic Element MatriX (FLEX ® ) family combines the  benefits of both erasable programmable logic devices (EPLDs) and field-programmable gate arrays (FPGAs). The FLEX8000 device family is ideal for a variety of applications because it combines the fine-grained architecture and high register count characteristics of FPGAs with the high speed and predictable interconnect delays of EPLDs. Logic is implemented in LEs that include compact 4-input look-up tables (LUTs) and programmable registers. High performance is provided by a fast, continuous network of routing resources. JTAG BST circuitryYesNoYesYesNoYes Table 2.FLEX8000 Package Options & I/O Pin Count  Note (1)  Device 84-Pin PLCC100-Pin TQFP144-Pin TQFP160-Pin PQFP160-Pin PGA192-Pin PGA208-Pin PQFP225-Pin BGA232-Pin PGA240-Pin PQFP280-Pin PGA304-Pin RQFP EPF8282A6878EPF8282AV78EPF8452A6868120120EPF8636A68118136136EPF8820A112120152152152EPF81188A148184184EPF81500A181208208  Altera Corporation 3FLEX 8000 Programmable Logic Device Family Data Sheet F  L  E  X   8   0   0   0   3 FLEX8000 devices provide a large number of storage elements for applications such as digital signal processing (DSP), wide-data-path manipulation, and data transformation. These devices are an excellent choice for bus interfaces, TTL integration, coprocessor functions, and high-speed controllers. The high-pin-count packages can integrate multiple 32-bit buses into a single device. Table3 shows FLEX8000 performance and LE requirements for typical applications.All FLEX8000 device packages provide four dedicated inputs for synchronous control signals with large fan-outs. Each I/O pin has an associated register on the periphery of the device. As outputs, these registers provide fast clock-to-output times; as inputs, they offer quick setup times.The logic and interconnections in the FLEX8000 architecture are configured with CMOS SRAM elements. FLEX8000 devices are configured at system power-up with data stored in an industry-standard parallel EPROM or an Altera serial configuration devices, or with data provided by a system controller. Altera offers the EPC1, EPC1213, EPC1064, and EPC1441 configuration devices, which configure FLEX8000 devices via a serial data stream. Configuration data can also be stored in an industry-standard 32K ×  8bit or larger configuration device, or downloaded from system RAM. After a FLEX8000 device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Because reconfiguration requires less than 100 ms, real-time changes can be made during system operation. For information on how to configure FLEX8000 devices, go to the following documents: ■ Configuration Devices for APEX & FLEX Devices Data Sheet ■ BitBlaster Serial Download Cable Data Sheet ■ ByteBlasterMV Parallel Port Download Cable Data Sheet ■  Application Note 33 (Configuring FLEX8000 Devices) ■  Application Note 38 (Configuring Multiple FLEX8000 Devices) Table 3.FLEX8000 Performance  Application LEs Used Speed Grade UnitsA-2 A-3 A-4 16-bit loadable counter161259583MHz16-bit up/down counter161259583MHz24-bit accumulator24876758MHz16-bit address decode44.24.96.3ns16-to-1 multiplexer106.67.99.5ns  4Altera CorporationFLEX 8000 Programmable Logic Device Family Data Sheet FLEX8000 devices contain an optimized microprocessor interface that permits the microprocessor to configure FLEX8000 devices serially, in parallel, synchronously, or asynchronously. The interface also enables the microprocessor to treat a FLEX8000 device as memory and configure the device by writing to a virtual memory location, making it very easy for the designer to create configuration software.The FLEX8000 family is supported by Altera’s MAX+PLUSII development system, a single, integrated package that offers schematic, text—including the Altera Hardware Description Language (AHDL), VHDL, and Verilog HDL—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUSII software provides EDIF 2 0 0 and 3 0 0, library of parameterized modules (LPM), VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and UNIX workstation-based EDA tools. The MAX+PLUSII software runs on Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. The MAX+PLUSII software interfaces easily with common gate array EDA tools for synthesis and simulation. For example, the MAX+PLUSII software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the MAX+PLUSII software contains EDA libraries that use device-specific features such as carry chains, which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the MAX+PLUSII development system includes DesignWare functions that are optimized for the FLEX 8000 architecture. f For more information on the MAX+PLUSII software, go to the  MAX+PLUSII Programmable Logic Development System & Software Data Sheet . Functional Description The FLEX8000 architecture incorporates a large matrix of compact  building blocks called logic elements (LEs). Each LE contains a 4-input LUT that provides combinatorial logic capability and a programmable register that offers sequential logic capability. The fine-grained structure of the LE provides highly efficient logic implementation.Eight LEs are grouped together to form a logic array block (LAB). Each FLEX8000 LAB is an independent structure with common inputs, interconnections, and control signals. The LAB architecture provides a coarse-grained structure for high device performance and easy routing.

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Jul 23, 2017
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