Design and Development of Gaussian Minimum Shift Keying (GMSK) Demodulator for Satellite Communication

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Bonfring International Journal of Research in Communication Engineering Volume 2, Issue 2, 2012
  Bonfring International Journal of Research in Communication Engineering, Vol. 2, No. 2, June 2012 6 ISSN 2277 - 5080 | © 2012 Bonfring Abstract---    This paper discusses DSP based implementation of Gaussian Minimum Shift Keying (GMSK) demodulator using Polarity type Costas loop. The demodulator consists of a Polarity type Costas loop for carrier recovery, data recovery, and phase detection. Carrier has been recovered using a loop of center-frequency locking  scheme as in M-ary Phase Shift Keying (MPSK) Polarity type Costas-loop. Phase unwrapping and Bit-Reconstruction is  presented in detail. All the modules are first modeled in  MATLAB (Simulink) and Systemview. After bit true simulation, the design is coded in VHDL and code simulation is done using QuestaSim 6.3c. The design is targeted to Virtex-4  XC4VSX35-10FF668 Xilinx FPGA (Field programmable gate array) for real time testing, which is carried out on Xtreme  DSP development platform. Keywords---     Nyquist Filter, Bandwidth-Time Product,  Inter-Symbol-Interference (ISI), Phase Wrapping, Phase Unwrapping I.   I  NTRODUCTION  Major requirement of satellite communication system is to reduce the amount of required transmission power and  bandwidth. As the available resource is power and bandwidth, often a trade-off is made between the power and bandwidth  based on a particular application. Gaussian Minimum Shift Keying (GMSK) provides the best performance in terms of the required bandwidth and the required power for the transmission. After several years of research effort, the Consultative Committee for Space Data Systems (CCSDS) has mandated the exclusive use of GMSK with bandwidth-time product BTb = 0.5 for all interplanetary missions with transmitted bit rates higher than 2 Mbps. For near-Earth missions, instead, GMSK with BTb = 0.25 is one of the recommended CCSDS options, thereby potentially allowing for the same demodulator for interplanetary and non- interplanetary missions[1]. Gaussian Minimum Shift Keying (GMSK) has been the most common modulation format belonging to the class of  partial response Continuous Phase Modulation (CPM) scheme. It is primarily adopted in the GSM standards for land mobile radio communication systems with BT  b  = 0.3 because of its  Pradeep Kumar Govindaiah, PG Scholar, Digital Electronics and Communication, Department of Electronics and Communication, MVJ College of Engineering, Whitefield, Bengaluru. E-mail:   high bandwidth efficiency and constant envelope modulation characteristics which reduces the required power. II.   M ATHEMATICAL A SPECTS OF GMSK    M ODULATOR AND D EMODULATOR     A.   GMSK Modulator    GMSK is ― Gaussian filtered MS K‖  is a form of continuous phase modulation, in which the input bits with, rectangular (+1, -1) shaping is converted to Gaussian pulses  by a Gaussian low-pass filter which is a non-Nyquist filter  before further modulation by a frequency modulator. Due to the use of a non-Nyquist Gaussian filter the input  pulses overlap, giving rise to a phenomenon known as Inter-Symbol Interference (ISI). The extent of this overlap is determined by the product of the bandwidth of the Gaussian filter and the data-bit duration (BT product). Due to ISI the spectrum becomes compact thus, increasing bandwidth efficiency. Even though we may have to supply an additional  power by an amount of 6 dB to counter ISI at the demodulator it meets the requirements of ACI (the GMSK spectrum has the first side lobe which gives an attenuation of 40-60 dB) and gives a compact spectrum due to the introduction of ISI so that more channels can be placed in the available  bandwidth. One of the efficient algorithms for the implementation of GMSK Modulator is the Quadrature modulator structure. This structure consists of two major blocks, a quadrature base-band  processor followed by I/Q Modulator. The modulation index can be exactly maintained at m=0.5 with this method[2]. The  block diagram of Quadrature modulator structure is as shown in figure 1. The GMSK Signal generated using the above Quadrature Structure is given by (1) )tf 2sin()t(Q)tf 2cos()t(I)t(s cc Pradeep Kumar Govindaiah Design and Development of Gaussian Minimum Shift Keying (GMSK) Demodulator for Satellite Communication A  Bonfring International Journal of Research in Communication Engineering, Vol. 2, No. 2, June 2012 7 ISSN 2277 - 5080 | © 2012 Bonfring Figure 1: GMSK Modulator (Quadrature Structure)  B.   GMSK Demodulator A variety of different types of receivers exist for coherent detection of GMSK signal. The demodulator can be implemented in different optimum and sub-optimum methods. In this paper demodulation of GMSK signal is carried out considering as a partial response continuous phase modulation signal[6]. If the GMSK signal is considered as a partial response continuous phase modulation signal (with modulation index of 1/2), then the receiver is made of an ideal multiplier that multiplies the received signal with a locally generated carrier, followed by low-pass filters to generate the real and imaginary  parts of the complex envelope of the received signal. Then a  phase generator builds all the possible phase transitions, finally the bits are reconstructed. Figure 2: Block Diagram of I & Q Implementation of GMSK Demodulation The Costas loop performs both phase-coherent suppressed carrier reconstruction and synchronous data detection within the loop. The upper loop is referred to as the quadrature, or tracking loop, and functions as a typical PLL, providing a data-corrupted error signal, Z c (t). The lower in-phase, or decision loop provides data extraction at the output of the lower mixer, and corrects the data corruption of Z c (t). The corrected error signal, Z o (t), is applied through loop filter F(s) to the VCO, which yields a phase estimate and generate the carrier signal[11].   A modified (hard-limited) Costas loop used for the demodulation of GMSK signals is shown in Figure 3. Figure 3: Polarity Type Costas Loop for Carrier Recovery From equation (1) we have the GMSK signal using I-Q modulation methods, , (2) The received signal under ideal conditions, can be given as, ))(2sin()())(2cos()()(  t t   f  t Qt t   f  t  I t  s d cd c   (3)   where, )t( d  is the frequency deviation occurred due to channel characteristics. The output of PD1 is given as )t(s)t(tf 2cos( oc  (4) where )t( o  is the initial offset in the VCO of the carrier recovery loop. ))]t(tf 2sin()t(Q))t(tf 2cos()t(I[))t(tf 2cos( dcdcoc  (5) ))]()(   cos())()(4[cos( 2)( t t t t t   f   t  I  d od oc   ))]t()t(sin())t()t(tf 4[sin( 2)t(Q dodoc   (6) The output of PD2 is given by )t(s)t(tf 2sin( oc  (7) ))]t(tf 2sin()t(Q))t(tf 2cos()t(I[))t(tf 2sin( dcdcoc  (8) ))]()(sin())()(4[sin( 2)( t t t t t   f   t  I  d od oc   )tf 2sin()t(Q)tf 2cos()t(I)t(s cc  Bonfring International Journal of Research in Communication Engineering, Vol. 2, No. 2, June 2012 8 ISSN 2277 - 5080 | © 2012 Bonfring ))]()(cos())()(4[cos( 2)( t t t t t  f   t Q d od oc   (9)   Passing signals of equation (9) the I-arm and Q-arm  becomes I-arm component, ))]t()t([sin( 2)t(Q ))]t()t([cos( 2)t(I )t(i dodo  (10) Q-arm component, ))]t()t([cos( 2)t(Q ))]t()t([sin( 2)t(I )t(q dodo  (11) the error signal applied through loop filter F(s) to VCO is given by )}t(i)]t(qsgn[)t(q)]t(i{sgn[e GMSK    (12)   I_rec and Q_rec components are obtained at the output of the Low-pass filters of I-arm and Q-arm respectively as shown in the figure 3, the phase information is obtained by arctan operation. The phase information obtained is wrapped phase information, which has to be unwrapped before performing the differentiation. The wrapped phase information lies between + to  –  . III.   R  ELATED W ORK SECTION :   U  NWRAPPING THE P HASE O BTAINED FROM ARC   T AN O PERATION Unwrapping of the phase obtained is performed by the following steps given below and as shown in figure 4. Step 1.  Differentiating the wrapped phase which gives the glitches extended to both positive and negative sides of the data obtained. Step 2.  Detection of the positive and negative glitches is done. Step 3.  Set and reset circuit to generate the control signal to the up down counter. Step 4.  Positive glitches detection is given to the set circuit and negative glitches detection is given to the Reset circuit as shown in the figure 5. Step 5.  Output of the Set and Reset circuit is given to control input of the up down counter which generates the multiples of 2*pi which is to be added to wrapped phase to obtain the unwrapped phase. Step 6.  Finally the unwrapped phase is differentiated to recover the data. Figure 4: Phase Unwrapping and Bit Reconstruction The set and reset Logic is as given in figure 5. Figure 5: Set and Reset Logic IV.   I  N -P HASE /   MID-P HASE S YNCHRONIZER ( FOR C LOCK R  ECOVERY ) This bit synchronizer also refers as Data transition tracking loop (DTTL)[4]. It operates in a closed loop and combines the operations of bit detection and bit synchronization. The In  phase / Mid Phase synchronizer is employed at low SNR and medium data rates. It also operates well even in the presence of re latively long one’s and zero’s.  The In phase branch determines the polarity of the bit transition, when and if they occur, while the mid phase channel determines the magnitude of the bit-timing error. Use of both channels in the multiplier provides the correct sign of the timing error. The filtered output of the multiplier is used to drive the Numerically Controlled Oscillator (NCO) and timing circuit is designed to control the integrate-and-dump operations as shown in figure 6. It is possible to improve noise  performance while SNR is above threshold by narrowing the mid phase integration window to T/4[4].  Bonfring International Journal of Research in Communication Engineering, Vol. 2, No. 2, June 2012 9 ISSN 2277 - 5080 | © 2012 Bonfring Figure 6: Inphase and Midphase Synchronizer (DTTL)   The bit synchronizer can be modeled as a PLL with feedback system as shown in figure 7. Given the requirement of bit synchronizer in terms of natural frequency ω n  and damping factor ξ , system can be modeled in terms of K   pd , Kvco ,  K1 and K2 which are defined below. The close loop transfer function of above loop is given by. S)s(F K K 1S)s(F K K )s(CLTF VCO pdVCO pd  (13) where,  pd K   = Phase detector gain in Volts/radian VCO K  = Sensitivity of VCO in rad/sec/volts )s(F  = Loop filter transfer function VCO pd K K K   (14) The equation (13) can be written as, )s(KFS )s(KF S)s(F K 1S)s(F K )s(CLTF  (15) Figure 7: Phase Locked Loop Depending on the choice of F(s), the CLTF(s) can be either first or second order system. For example, for type-2 systems, loop filter structure is shown in figure 8. Where, s2K 1K )s(F , (16) Figure 8: Loop Filter Substituting equation (16) in equation (15), becomes 2K *K s1K K s 2K *K s1K K  )s(CLTF 2  (17) which is of type 2, 2 nd  order system. Using servo theory, equation (17) is of the form 2nn22nn s2ss2  (18) Where, VCO pd K K K   (19) The value of  pd K  and VCO K  depends on S f   and the magnitude of the accumulator. The value of K1 and K2 can be calculated by 2K K K  VCO pdn  (20) nVCO pd 21K K K   (21) The equations (13) to (21) are sufficient to model the bit synchronizer, and by changing the value of K1 and K2 we can control the performance and characteristics of demodulator loop. The stability of the system can be verified by transforming S-domain closed loop transfer function to Z-domain[4]. V.   M ATLAB S IMULATION AND R  ESULTS  Figure 9: PN Sequence
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