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  Stellaris  ®  LM3S6965 Microcontroller  DATA SHEET Copyright  ©   2007-2012Texas Instruments IncorporatedDS-LM3S6965-12746.2515SPMS144H TEXAS INSTRUMENTS-PRODUCTION DATA NRND: Not recommended for new designs.  Copyright Copyright  ©  2007-2012 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare  ®  are registered trademarks of Texas InstrumentsIncorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others.PRODUCTION DATA information is current as of publication date. Products conform to specications per the terms of Texas Instruments standardwarranty. Production processing does not necessarily include testing of all parameters.Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductor  products and disclaimers thereto appears at the end of this data sheet.Texas Instruments Incorporated108 Wild Basin, Suite 350Austin, TX 78746http://www.ti.com/stellarishttp://www-k.ext.ti.com/sc/technical-support/product-information-centers.htm June 18, 2012 2 Texas Instruments-Production Data NRND: Not recommended for new designs.  Table of Contents Revision History .............................................................................................................................25About This Document ....................................................................................................................31  Audience .............................................................................................................................................. 31 About This Manual ................................................................................................................................ 31Related Documents ............................................................................................................................... 31Documentation Conventions .................................................................................................................. 32 1 Architectural Overview .......................................................................................... 34 1.1 Product Features .......................................................................................................... 341.2 Target Applications ........................................................................................................ 431.3 High-Level Block Diagram ............................................................................................. 431.4 Functional Overview ...................................................................................................... 451.4.1 ARM Cortex™-M3 ......................................................................................................... 451.4.2 Motor Control Peripherals .............................................................................................. 461.4.3 Analog Peripherals ........................................................................................................ 471.4.4 Serial Communications Peripherals ................................................................................ 471.4.5 System Peripherals ....................................................................................................... 491.4.6 Memory Peripherals ...................................................................................................... 501.4.7 Additional Features ....................................................................................................... 501.4.8 Hardware Details .......................................................................................................... 51 2 The Cortex-M3 Processor  ......................................................................................52 2.1 Block Diagram .............................................................................................................. 532.2 Overview ...................................................................................................................... 542.2.1 System-Level Interface .................................................................................................. 542.2.2 Integrated Configurable Debug ...................................................................................... 542.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 552.2.4 Cortex-M3 System Component Details ........................................................................... 552.3 Programming Model ...................................................................................................... 562.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 562.3.2 Stacks .......................................................................................................................... 562.3.3 Register Map ................................................................................................................ 572.3.4 Register Descriptions .................................................................................................... 582.3.5 Exceptions and Interrupts .............................................................................................. 712.3.6 Data Types ................................................................................................................... 712.4 Memory Model .............................................................................................................. 712.4.1 Memory Regions, Types and Attributes ........................................................................... 732.4.2 Memory System Ordering of Memory Accesses .............................................................. 732.4.3 Behavior of Memory Accesses ....................................................................................... 732.4.4 Software Ordering of Memory Accesses ......................................................................... 742.4.5 Bit-Banding ................................................................................................................... 752.4.6 Data Storage ................................................................................................................ 772.4.7 Synchronization Primitives ............................................................................................. 782.5 Exception Model ........................................................................................................... 792.5.1 Exception States ........................................................................................................... 802.5.2 Exception Types ............................................................................................................ 802.5.3 Exception Handlers ....................................................................................................... 83 3June 18, 2012 Texas Instruments-Production DataStellaris ®  LM3S6965 Microcontroller  NRND: Not recommended for new designs.  2.5.4 Vector Table .................................................................................................................. 832.5.5 Exception Priorities ....................................................................................................... 842.5.6 Interrupt Priority Grouping .............................................................................................. 852.5.7 Exception Entry and Return ........................................................................................... 852.6 Fault Handling .............................................................................................................. 872.6.1 Fault Types ................................................................................................................... 882.6.2 Fault Escalation and Hard Faults .................................................................................... 882.6.3 Fault Status Registers and Fault Address Registers ........................................................ 892.6.4 Lockup ......................................................................................................................... 892.7 Power Management ...................................................................................................... 892.7.1 Entering Sleep Modes ................................................................................................... 902.7.2 Wake Up from Sleep Mode ............................................................................................ 902.8 Instruction Set Summary ............................................................................................... 91 3 Cortex-M3 Peripherals ........................................................................................... 94 3.1 Functional Description ................................................................................................... 943.1.1 System Timer (SysTick) ................................................................................................. 943.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................... 953.1.3 System Control Block (SCB) .......................................................................................... 973.1.4 Memory Protection Unit (MPU) ....................................................................................... 973.2 Register Map .............................................................................................................. 1023.3 System Timer (SysTick) Register Descriptions .............................................................. 1043.4 NVIC Register Descriptions .......................................................................................... 1083.5 System Control Block (SCB) Register Descriptions ........................................................ 1213.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 148 4 JTAG Interface ......................................................................................................158 4.1 Block Diagram ............................................................................................................ 1594.2 Signal Description ....................................................................................................... 1594.3 Functional Description ................................................................................................. 1604.3.1 JTAG Interface Pins ..................................................................................................... 1604.3.2 JTAG TAP Controller  ................................................................................................... 1624.3.3 Shift Registers ............................................................................................................ 1634.3.4 Operational Considerations .......................................................................................... 1634.4 Initialization and Configuration ..................................................................................... 1664.5 Register Descriptions .................................................................................................. 1664.5.1 Instruction Register (IR) ............................................................................................... 1664.5.2 Data Registers ............................................................................................................ 169 5 System Control .....................................................................................................171 5.1 Signal Description ....................................................................................................... 1715.2 Functional Description ................................................................................................. 1715.2.1 Device Identification .................................................................................................... 1725.2.2 Reset Control .............................................................................................................. 1725.2.3 Power Control ............................................................................................................. 1765.2.4 Clock Control .............................................................................................................. 1775.2.5 System Control ........................................................................................................... 1825.3 Initialization and Configuration ..................................................................................... 1835.4 Register Map .............................................................................................................. 1845.5 Register Descriptions .................................................................................................. 185 June 18, 2012 4Texas Instruments-Production DataTable of Contents NRND: Not recommended for new designs.
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