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Microprocessor History

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Microprocessor History 4004 through Core i7
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  4040 8008 8080 8086 8088 4004   1 st   µp in the world 4-bit microprocessor Single-chip IC processor 4-bit memory locations Contains 45 instructions 50 KIPS P-MOSFET Technology 12-bit addresses  Appear in video games and small control Sys. (Microwave ovens) most calculators based on 4-bit µp P-MOS technology 60 KIPS 4-bit microprocessor 13-bit addresses P-MOSFET Evolution of 4-bit µp ended when Intel released 4040 Improvement in speed , word-width and memory size 8-bit microprocessor 14-bit addresses Memory size 16 KB Contain 48 instructions N-MOS technology 8-bit microprocessor Memory size 64 KB 10x faster than 8008 TTL Compatible N-MOS technology TTL compatible in 8080 8008 was not directly compatible This made interfacing easier and less expensive for 8080 The last 8-bit µp 769,230 IPS N-MOS technology Contains 246 inst. Main advantage its internal clock generator  , system controller and higher clock frequency 16-bit microprocessor  2.5 MIPS 1 MB of memory 4 or 6 byte inst. Cache  ∘  of inst. Over 20 K  µp called CISC. Instructions set included multiply and divide instructions. IBM chose 8080 in its PC. TTL Compatible Means that the o/p of one TTL device can be used to drive the i/p of the other TTL.    16-bit µ  p  means µ  p can read 16-bit of data in one clock cycle   8085 Identical to 8086 except  for its 8-bit external bus  80586P5 80486 80386 80286 P MMX Pentium Pro Pentium II  Almost Identical to 8086/8088 16 MB Memory 4 MIPS 32-bit µp 4 GB of memory 80386SL 80386SLC 80386SX 80386EX  Addressable memory= 16 MB , 16-bit data bus , 24-bit address bus    Addressable memory= 32 MB , 16-bit data bus , 25-bit    address bus   Called “Embedded PC” , Computer on a single IC 16-bit data bus and 26-bit address 32-bit µp 50 MIPS Level 1 cache 8 K 80486DX2 Executed instructions at 66 MHz with memory transfers at 33 MHz (Double-Clocked µp)   Triple-Clocked Executed instructions at 100 MHz with memory transfers at 33 MHz    16 KB L1 Cache (8 KB of instruction cache + 8 KB of data Cache.) 4 GB memory Data bus width 64-bit Data bus speed 60 or 66 MHz  Address bus 32-bit 57 instructions 32 KB L1 Cache bus clock rate   66 MHz Improve performance on multimedia tasks, such as encoding and decoding digital media data Wider data bus includes double-precision floating-point used in high-speed and Graphical Display. Executes two instructions not dependent on each other per clocking period. Super-scale Technology (improve performance ). Pentium Named P6 Clock frequency 150 MHz 16 KB L1 cache  256 KB L2 cache Execute 3 inst. At a time Used for server market 32-bit processor 4 GB memory (32-bit add) 64 GB memory(36-bit add Pentium Pro with MMX. 512 KB L2 Cache  Core2 Pentuim 4 Pentuim III Xeon Core i3 Core i5 Core i7 32 KB L1 Cache 512K , 1M ,2M L2 Cache Designed for High-end workstation and     server app   Clock Freq. up to 1 GHz  Available in 2 versions Memory runs at 100 MHz 512 KB cache , runs at    clock speed , use 100 MHz memory bus   256 KB cache , runs at clock speed , use 100 MHz memory bus   Uses Intel P6 architecture Pentium 4 speed 3.2 GHz Core2 speed 3 GHz Use 45 nm Technology Use C-MOSFET Use Copper inside processor instead of Aluminum 64-bit processor (2 physical cores / 4 threads) 64 KB L1 Cache 512 KB L2 Cache 4 MB L3 Cache Socket 1156 LGA 64-bit processor 4 physical cores 64 KB(per core) L1 Cache  265 KB(per core) L2 Cache 8 MB L3 Cache Socket 1156 LGA 64-bit processor 4 physical cores  265 KB L1 Cache 8 MB L3 Cache Socket 1366 LGA     A CPU socket or CPU slot is a mechanical component(s) that provides mechanical and electrical connections between a microprocessor and a printed circuit board (PCB) Slot 1 Version Flip-Chip Version

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Jul 23, 2017
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