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r c PROCEEDINGS vde-verlag 2nd European Test Conference Munich, April 10-12,1991 UB/TIB Hannover

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r c o n J 2nd European Test Conference Munich, April 10-12,1991 PROCEEDINGS vde-verlag UB/TIB Hannover Table of contents Session 1: Compatible Test Chips Chair: K. Parker, Hewlett-Packard,
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r c o n J 2nd European Test Conference Munich, April 10-12,1991 PROCEEDINGS vde-verlag UB/TIB Hannover Table of contents Session 1: Compatible Test Chips Chair: K. Parker, Hewlett-Packard, USA Co-ordinator: C. Maunder, BTRL, UK Paper 1.1: The Boundary-Scan Master: Architecture and Implementation 1 N. Jarwala, C. W. Yau AT & T Bell Labs. USA Paper 1.2: Self-Test of a 256 k x 4 bit Stand-Alone Static RAM 11 R. H. A. Rijk, R. W. C. Dekker, H. G. Kerkhoff University of Twente, The Netherlands Paper 1.3: Boundary Scan and BIST Compatible IEEE : VHDL & Autosynthesis Design of a SRAM Tester Macrocell and Chip 17 S. Kritter, E. Mackowiak SGS-Thomson Microelectronics, France Session 2: Stimuli Generation and Signature Analysis in BIST Structures Chair: 7: IV. Williams, IBM, USA Co-ordinator: E. Aas, Trondheim University, Norway Paper 2.1: LFSR based Deterministic and Pseudo-Random Test Pattern Generator Structures 27 C. Dufaza, G. Cambon LAMM, France Paper 2.2: IC Realization of a Cellular Automata Based Self-Test Strategy for Programmable Data Paths 35 J. van Sas, F. Catthoor, S. Vernalde IMEC Laboratory, Belgium Paper 2.3: Experimental Analysis of Fault Coverage in Systems with Signature Registers 45 J. Rajski, J. Tyszer McGill University, Canada Session 3: BIST of Regular Structures Chair: V. Yarmolik, Minsk Radio Eng. Institute, USSR Co-ordinator: J.-L Becu, SGS-Thomson Microelectronics, France Paper 3.1: A Universal Test Algorithm for the Self-Test of Parametrizable Random Access Memories 53 H. C. Ritter, Th. M. Schwair Siemens, Germany Paper 3.2: Test Pattern Generators for Arithmetic and Logic Units 61 M. Nicolaidis IMAG/TIM3, France Paper 3.3: Parallel Self-Test and the Synthesis of Control Units 73 B. Eschermann, H. -J. Wundetlich Karlsruhe University, Germany Session 4: Advances in IC Defects-Based Testability Chair: C. Hawkins, University of New Mexico, USA Co-ordinator: C. Landrault, LAMM, France Paper 4.1: Defect and Design Error Diagnosability Measure W. Maly, S. Naik Carnegie Mellon University, USA 83 Paper 4.2: Quantifying Non-Target Defect Detection by Target Fault Test Sets 91 K. M. Butler, M. R. Mercer Texas University, USA Paper 4.3: Layout-Driven Testability Enhancement 101 J. P. Teixeira, F. M. Concalves, J. J. T. Sousa INESC, Portugal Session 5: Board and System Fault Location Chair: M. Mezzalama, Politecnico di Torino, Italy Co-ordinator: D. Laurent, Bull Systems, France Paper 5.1: Test Data Collecting System: A Paperless Test, Troubleshoot and Repair L Daemen Alcatel Bell, Belgium Paper 5.2: Troubleshooting Digital Circuit Boards by Means of an Expert System: An Approach at Alcatel Bell 123 J. Vanwelkenhuysen Vrije University, Belgium Paper 5.3: Distributed Diagnosis of Faults in a Multiple-Path Multi-Stage Interconnection Network 133 S-J. Wang Princeton University, USA Session 6: Advances in CMOS/BICMOS Testing Chair: W. Maly, Carnegie-Mellon University, USA Co-ordinator: C. Lopez-Barrio, Telefonica I + D, Spain Paper 6.1: Fault Modelling of Gate Oxide Shorts Gloating Gate and Bridging Failures in CMOS Circuits 143 V. H. Champac, R. Rodriguez-Montane's, J. A. Segura, J. Figueras, J. A. Rubio UPC, Spain Paper 6.2: Comparing Stuck Fault and Current Testing via CMOS Chip Test 149 T. Storey, W. Maly, J. Andrews, M. Miske Carnegie Mellon University, National Semiconductor, USA Paper 6.3: Failure Mechanisms in BiCMOS Sea-of-Gate Arrays W. Denner, G. Troster, A. Wedel, E. Zocher Telefunken, Germany 157 Session 7: High-Performance Fault Simulation Chair: M. Kessler, IBM Deutschland, Germany Co-ordinator: M. Melgara, CSELT, Italy Paper 7.1: Vector Length Control for Compiled Code Event Driven Pattern Parallel Fault Simulation W. Daehn, D. Kannemacher, J. Castagne Hannover University, Germany Paper 7.2: An Efficient Parallel Pattern Gate Delay Fault Simulator with Accelerated Detected Fault Size Determination Capabilities F. Fink, K. Fuchs, M. H. Schulz TU Munich, Siemens, Germany Paper 7.3: Switch-Level Fault Simulation by Critical Path Tracing M. Dalpasso, M. Favalli, P. Olivo, B. Ricco Bologna University, Italy Session 8: Standards for Test-Information Interchange Chair: H. Wojtkowiak, University of Siegen, Germany Co-ordinator: M. Wahl, University of Siegen, Germany Paper 8.1: A User's Introduction to WAVES 191 R. Hillman, F. Koo, L Shombert RADC, Hughes Aircraft, Harris Corporation, USA Paper 8.2: EDIF as a Standard Test Specification Format 201 P. Vandeloo IMEC, Belgium Paper 8.3: An Automatic Test Program Generation Strategy Using a Tester-Independent Waveform Representation 209 Louis Testa, R. Lunde TSSI, Beaverton, USA Session 9: Fault Simulation and ATPG Chair: C. Almeida, INESC, Portugal Co-ordinator: M. Schulz, Siemens-Nixdorf, Germany Paper 9.1: Testing Finite State Machines Implemented by Programmable Logic Devices 217 F. Corsi, S. Martino, A. L. Sangiovanni-Vincentelli Bari University, Italy; Berkeley University, USA Paper 9.2: Distributed Fault Simulation with Vector Set Partitioning 227 A. Warshawsky, J. Rajski McGill University, Canada Paper 9.3: LFSR-Coded Test Patterns for Scan Designs 237 B. Koenemann IBM, USA Session 10: Scan Optimisation Techniques Chair: J. Jamieson, Alcatel, Belgium Co-ordinator: F. Beenker, Philips Research, The Netherlands Paper 10.1: A Model for Test-Time Reduction of Scan Testable Circuits 243 S. Oosdikj, F. Beenker, L. Thijssen Philips Research Labs, Delft University, The Netherlands Paper 10.2: Test Point Insertion for Scan-Based BIST 253 B. H. Seiss, P. M. Trouborst, M. H. Schulz TU Munich, Germany; Bell-Northern Research, Canada; Siemens, Germany Paper 10.3: A Methodology for Partial Scan Design 263 D. Pradhan, S. Nori, J. Swaminathan Massachusetts University, Amdahl Corp., USA Session 11: Advanced ATPG Chair: G. Saucier, INPG/CSI, France Co-ordinator: E. Trischler, Siemens-Nixdorf, Germany Paper 11.1: Mixed Level Automatic Test Pattern Generation for CMOS Circuits 273 M. L Flottes, C. Landrault, S. Paul, S. Pravossoudovitch LAMM, France Paper 11.2: MINOTAUR A Mixed Level Test Pattern Generator for VLSI Circuits J. M. C. Geada, G. Russell Newcastle upon Tyne University, UK Paper 11.3: Advanced Techniques for Sequential Test Generation 293 N. Gouders, R. Kaibel Duisburg University, Germany Session 12: Analogue and Mixed-Signal Testing Chair: K. Baker, Philips Research Labs., The Netherlands Co-ordinator: J.-P. Teixeira, INESC, Portugal Paper 12.1: A Novel Technique for Testing Mixed-Signal I. C.'s 301 P. S. Evans, M. A. Al-Qutayri, P. R. Shepherd Bath University, UK Paper 12.2: Hybrid Built-in Self-Test (HBIST) for Mixed Analogue/Digital Integrated Circuits 307 M. J. Ohletz Hannover University, Germany Paper 12.3: Automatic Test of T1 and CEPT Line Interface Units 317 D. J. Derian LTX, USA Session 13: Testable Design through Testability Analysis Chair: J. Soden, Sandia Labs., USA Co-ordinator: P. Prinetto, Politecnico di Torino, Italy Paper 13.1: Hierarchical Functional Level Testability Analysis 327 B. H. Nairn, B. Kaminska Montreal Polytechnic, Canada Paper 13.2: On Bridging Fault Controllability and Observability and Their Correlations to Detectability 333 R. Kapur, K. M. Butler, M. R. Mercer Texas University, USA Paper 13.3: Trade-off Analysis of the Effectiveness of Testability Estimators 341 R. Kapur, J. Ferguson, M. Abadir Texas University, USA Session 14: High-Performance Fixturing in IC Testing Chair: A. Wakeling, Schlumberger, UK Co-ordinator: F. Pool, Philips Components, The Netherlands Paper 14.1: Impedance Matching Circuit for Dynamic Correction of Device/ATE Impedance Mismatch 351 M. C. Kohalmy Teradyne, USA Paper 14.2: High Speed Fixturing of Chips and Wafers for Electron Beam Probing K. Helmreich, M. Chowanetz Erlangen-Nurnberg University, Germany Paper 14.3: Groundbounce in ASIC's: Modelling and Test Results 367 L Diaz-Olavarrieta Bell, Canada Session 15: Boundary Scan in Practice Chair: R. Tulloss, AT & T Bell Labs., USA Co-ordinator: C. Maunder, BTRL, UK Paper 15.1: A Test Economics Model & Cost-Benefit Analysis of Boundary Scan J. Miles, R. De Bondt, L. Daemen Alcatel Bell, Belgium Paper 15.2: Built-in Pad Test with Boundary Scan Schwederski, T. Buchner, J. Leenstra, G. Roos, L Spaanenburg Institute for Microelectronics Stuttgart, Germany Paper 15.3: Assessing Fault Coverage in Virtual Incircuit Testing of Partial Boundary-Scan.393 P. Hansen Teradyne USA Session 16: Test Pattern Preparation Chair: M. Gerner, Siemens, Germany Co-ordinator: W. Daehn, Sican, Germany Paper 16.1: Intent Documentation in a Graphical Test Programme Editor Simplifies the Logic Simulator Tester Link 397 R. W. Werthebach Braunschweig University, Germany Paper 16.2: Device-Oriented Test Program Generation using the Sequencer-Per-Pin Test System Architecture 405 C. Tinaztepe, P. David Schlumberger USA; Schlumberger France Paper 16.3: High Level Representation of ATE Patterns 413 A. R. Taylor LTX/Trillium, USA Session 17: Macrotest Tools and Techniques Chair: G. Robinson, GenRad, USA Co-ordinator: B. Courtois, IMAG/TIM3, France Paper 17.1: Interactive Test Strategy planning: Model and a Prototype 417 M. Laffitte Siemens, Germany Paper 17.2: Minimization of Test Control Blocks 427 E. J. Marinissen, R. Dekker Philips Research Labs, The Netherlands Paper 17.3: An Economics Based Test Strategy Planner for VLSI Design 437 C. Dislis, J. Dick, A. P. Ambler Brunei University, UK Paper 17.4: Automatic Test-Specification Generation for Macro-Level BIST Based on the Boundary-Scan Standard 447 R. P. van Riessen, H. G. Kerkhoff University of Twente, The Netherlands Session 18: Test System Architectures and Performance Chair: C. da Coste, Teradyne, Germany Co-ordinator: F. Pool, Philips Components, The Netherlands Paper 18.1: Performance Characteristics of a IGbps Digital Test System 455 D. C. Keezer South Florida University, USA Paper 18.2: Implementing Per-Pin Architecture VLSI for WLR EM parametric testing. 463 E. Weis, E. Kinsbron, A. Cohen, G. Chanoch, B. Vogel, N. Croitoru Tel Aviv University, Israel Paper 18.3: Remote Communications on the Tester Workstation 467 D. Dowding LTX/Trillium, USA Paper 18.4: Graphic Displays for Non-Graphic Test Data 473 A. E. Downey Ando Corporation, USA Posters Poster: Production Method Using IEEE Today 479 Jan - Erik Rickegard, Schlumberger ATE, Sweden Poster: Intelligent Probe Sample Placement 480 C. G. McKay, Schlumberger Technologies, UK Poster: Integrating Design for Test Through Concurrent Engineering Practical Implementations 481 Jon Turino, Logical Solutions Technology, Inc., USA Poster: On the Selection of a Partial Scan Path with Respect to Target Faults 482 Harald Gundlach, University Erlangen-Numberg, Germany Poster: The Design and Implementation of an Efficient Method to Generate Protocol Conformance Test Sequence 483 Johnny S. K. Wong, Iowa State University, USA Poster: CMOS Test Generation for High Fault Coverage by Switch Levelto Gate Level Coupling H. T. Vierhaus, GMD, Germany Poster: Pseudoexhaustive Test Sets Generated in LFSRs 485 Ondfej Novak, Technical Univ. of Liberec, Czechoslovakia Poster: A Fast Parallel Pattern Fault Simulator for Combinational Circuits 486 Dong S. Ha, Virginia Polytechnic Institute and State University, USA Poster: Test Generation for Digital Systems at Functional Level 487 Krzysztof Kuchcinski, Linkoping University, Sweden Poster: On Parallel Test Pattern Generation Algorithms 488 Tapan J. Chakraborty, AT & T Bell Laboratories, USA Poster: Logical Layer Conformance Testing of Parallel Bus Interfaces 489 Bemhard Muller, Forschungszentrum Informatik, Germany Poster: Modular Testing of a VLSI Processor Chip Using the BED System 490 Bernd Hanstein, Siemens, Germany Poster: An E-Beam Prober Based VLSI Device Characterization System 491 Peter Cundall, Schlumberger Technologies, USA Poster: An E-Beam Prober Based VLSI Device Characterization System 491 Peter Cundall, Schlumberger Technologies, USA Poster: VLSI Logic Verification Program Generator 492 Ajit Dingankar, Tien N. Le, IBM Corporation, USA Poster: Towards Functional Testing From a VHDL Data Flow Description 493 P. Wodey, Lab. de Genie Informatique, France Poster: Simplified Test Strategies for Analogue Integrated Circuits 494 A. P. Dorey, University of Lancaster, UK Poster: E-Beam Testing For Microprocessor Failure Location J. Cabestany, UPC, Spain Poster: Improved Probing in Analogue Diagnosis 496 Antony Wakeling, Schlumberger Technologies, UK Poster: Design & Test Integration 497 Ruedi H. Egger, GenRad, Switzerland Poster: Integral Test Strategy for Telecommunications Line-Cards 498 Dirk van de Lagemaat, Philips Communication Systems, The Netherlands Poster: A Hierarchical Test Generator for CMOS Bridging Faults 499 Will R. Moore, University of Oxford, UK Poster: Functional Model and Self-Testing in VHDL for Functional Test Generation 500 Heinz-Dieter Hummer, University of Duisburg, Germany Poster: PATSIM: An Automatic Test Pattern Generator in DISIM 501 Harbhajan Singh, Daimler-Benz, Germany Poster: A New Algorithm for Diagnosing Interconnect Faults on Boundary Scan Boards 502 Jose Manuel M. Ferreira, INESC, Portugal Poster: A New Prototype for ASIC Functional Testing 503 Carlos Beltan, INESC, Portugal Poster: A New Path Delay Fault Simulation Algorithm 504 Yuejian Wu, University of British Columbia, Canada Poster: Algorithms for VLSI Error Location Applied to an E-Beam Validation System 505 P. Garino, CSELT, Italy Poster: Timing Oriented Testing for VLSIs 506 Frank Dymann, Siemens, Germany Poster: Probability Driven Partial Scan Design 507 Chung Len Lee, National Chiao Tung University, Taiwan, R.O.C. Poster: Digital Simulators in Test; Conversion of Waveforms to Test Language 508 Gordon F. Taylor, GenRad, USA Poster: Using Emulation Techniques In General Purpose ATE 509 P.. Wade Williams, GenRad, USA Poster: Phoebus: A Tool for Hierarchical Testability and Redundancy Analysis 510 Jean-Claude Geffroy, INSAT/DGE/GERII, France Poster: Boundary Scan Design for a Memory Controller 511 Pefer L. Harrod, Advanced RISC Machines Ltd., UK Poster: Developments for Built-in-Self-Test of Mixed ASICs 512 Rosemary A. Cobley, Exeter University, UK Poster: Implementing Boundary-Scan and Pseudo-Random Built-in Self Test in a 0.7 Micron CMOS Asynchronous Transfer Mode Switch 513 P. Thorel, C.N.E.T., France Poster: Parsimonious Test Concept for Embedded PLAs in Boundary Scan Environment 514 EinarJ. Aas, Norwegian Inst. of Technology, Norway Poster: Towards Automated Diagnostic: E-Beam Tester Data Base Environment 515 Laurence Primot, IBM, France Poster: Tradeoffs in Self-Test and External Test of PLAs 516 EinarJ. Aas, Norwegian Inst. of Technology, Norway Poster: Simulation for Delay Faults 517 V. Xing, University of Twente, The Netherlands Poster: Hierarchical Approach to Test Pattern Generation 518 E. C. Weening, University of Twente, The Netherlands Poster: Autonomously Testable Dynamic CMOS PLAs 519 M. Renovell, LAMM, France Poster: A High-Level Pattern Development System Promoting Industrial Concurrent Engineering 520 Gunter T. Krampl, Siemens, Austria Poster: Automatic Test Pattern and Test Program Generation for VLSI Scan Designs 521 Friedrich Hapke, Philips Components, Germany Poster: Test of Analog Components in a Digital Environment 522 Martin Viktil, EB Technology, Norway Poster: Self-Checking Circuits in Presence of Bridging Faults. Possibilities of Current Sensing in XOR Parity Trees 523 Luz Balado, UPC, Spain Poster: Design for Contactless Testability in a Scan-Path Environment 524 Josef Gross, Universitat Hannover, Germany Poster: Spectrum Analysis of Small-Bandwidth Signals Using a Modulatet Electron Beam 525 W. Kern, SEL Alcatel, Germany Poster: Looking for Functional Fault Equivalence 526 Antonio Lioy, Politecnico di Torino, Italy Poster: An Application of Automata Theory to sequential ATPG 527 Paolo Prinetto, Politecnico di Torino, Italy Poster: Test Generation by Fault Sampling: Estimates of Population Coverage 528 Hassan Farhat, University of Nebraska, USA Poster: The Challenge of Designing a Tester that is Compatible and Different at the Same Time 529 John Doyle, GenRad, UK Poster: Implementing a Parallel/Serial Converter for Board Scan Test 530 Jay Brown, National Semiconductor, USA Poster: A Proposal for Extending the IEEE Standard Test Access Port to System Backplanes 531 Dilip Bhavasar, Digital Equipment, USA Poster: A Reduced Lost Fault Simulation Strategy for the AM29050 TM Microprocessor 532 Gopi Ganapathy, Advanced Micro Devices, USA
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