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SR Flip-Flop Design Report

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    SR Flip-Flop Waveform: =========================================================================== * Final Report * =========================================================================== Final Results : RTL Top Level Output File Name : SR_FF.ngr Top Level Output File Name : SR_FF Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics: # IOs : 5 Cell Usage : # BELS : 3 # LUT2 : 3 # FlipFlops/Latches : 2 # FDE : 2 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 4 # IBUF : 2 # OBUF : 2 Device utilization summary: Selected Device : 3s400tq144-5  Number of Slices: 2 out of 3584 0%  Number of Slice Flip Flops: 2 out of 7168 0%  Number of 4 input LUTs: 3 out of 7168 0%  Number of IOs: 5  Number of bonded IOBs: 5 out of 97 5% IOB Flip Flops: 2  Number of GCLKs: 1 out of 8 12% Partition Resource Summary:  No Partitions were found in this design.    Timing Report:  NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: Clock Signal | Clock buffer(FF name) | Load | clk | BUFGP | 2 | Asynchronous Control Signals Information:  No asynchronous control signals found in this design Timing Summary: Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: 3.529ns Maximum output required time after clock: 6.216ns Maximum combinational path delay: No path found Timing Detail: All values displayed in nanoseconds (ns) Timing constraint:  Default OFFSET IN BEFORE  for Clo   ck 'clk'  Total number of paths / destination ports: 8 / 4 Offset: 3.529ns (Levels of Logic = 2) Source: s (PAD) Destination: q (FF) Destination Clock: clk rising Data Path: s to q Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) IBUF:I->O 3 0.715 1.066 s_IBUF (s_IBUF) LUT2:I0->O 2 0.479 0.745 q_not00011 (q_not0001) FDE:CE 0.524 q Total 3.529ns (1.718ns logic, 1.811ns route) (48.7% logic, 51.3% route) Timing constraint:  Default OFFSET OUT AFTER   for Clock 'clk'  Total number of paths / destination ports: 2 / 2 Offset: 6.216ns (Levels of Logic = 1) Source: qbar (FF) Destination: qbar (PAD) Source Clock: clk rising Data Path: qbar to qbar Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) FDE:C->Q 1 0.626 0.681 qbar (qbar_OBUF) OBUF:I->O 4.909 qbar_OBUF (qbar) Total 6.216ns (5.535ns logic, 0.681ns route) (89.0% logic, 11.0% route) Total REAL time to Xst completion: 5.00 secs Total CPU time to Xst completion: 4.74 secs Total memory usage is 146144 kilobytes    RTL Schematic:   TTL Schematic: XPower Analyzer:    Power summary: | I(mA) | P(mW) | Total Vccint 1.20V | 15 | 19 | Total Vccaux 2.50V | 15 | 38 | Total Vcco25 2.50V | 0 | 0 | Inputs | 0 | 0 | Outputs | Vcco25 | 0 | 0 | Signals | 0 | 0 | Quiescent Vccint 1.20V | 15 | 19 | Quiescent Vccaux 2.50V | 15 | 38 |
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