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1. ES6425 Digital Media Processor 2 ESS Technology, Inc. Product Brief DESCRIPTION FEATURES ã Single-chip digital audio and video decoder and The ES6425 Digital Media…
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  • 1. ES6425 Digital Media Processor 2 ESS Technology, Inc. Product Brief DESCRIPTION FEATURES • Single-chip digital audio and video decoder and The ES6425 Digital Media Processor 2 (DMP2) is a high processor. performance single-chip audio/video decoder for a wide series of applications such as networked or non- • MPEG-4 Advanced Simple Profile* at full screen D1 video networked/flash memory media players. This second playback (playability is dependent on memory card generation of Digital Media Processor has an enhanced bandwidth). performance engine to decode MPEG-4 video at D1 • MPEG-2 video playback (playability is dependent on resolution with state-of-the-art progressive scan memory card bandwidth). NTSC/PAL video encoder for brilliant and sharp, flicker- • MPEG-1 video playback. free output to the video display. • Motion JPEG playback. At the heart of the ES6425 is the ESS proprietary Programmable Multimedia Processor core consisting of • JPEG photo playback. 32-bit RISC and 64-bit DSP processors that enable • Progressive JPEG photo playback. simultaneous parallel execution of system commands and • MP3 music playback. specialized multimedia decoding tasks. The ES6425 includes a memory controller which interfaces to 8-bit or • WMA music playback (Microsoft license required). 16-bit DRAM with up to 128-Mb capacity. • Dolby Digital decode (ES6425FDF only) The ES6425 performs video processing to provide high- • AAC audio decode and playback. resolution display of MPEG-1, MPEG-2, and MPEG-4 • ESS Music Slideshow. videos and JPEG photos. The integrated NTSC/PAL TV- encoder provides composite, S-video, and YUV outputs. • S/PDIF digital audio output. The ES6425 includes an On-Screen-Display (OSD) • Integrated NTSC/PAL encoder with pixel adaptive de- controller to provide a user friendly setup menu to enable interlacer and five 10-bit 54 MHz video DACs. or modify the various audio decoding and video display • High-quality progressive scan video output for flicker-free features. A CCIR656/601 digital video output port is also video display. present. • Simultaneous Composite, S-Video, and YUV outputs. The ES6425 also performs audio processing for Wave, • CCIR656/601 YUV 4:2:2 output. MP3, AAC, Dolby Digital, and WMA playback along with a 7-band graphic equalizer. The ES6425 has a multi- • On-Screen-Display controller with 3-bit blending to channel audio serial port compliant to I 2 S format for provide 256 colors display. interfacing to an external audio DAC and ADC. An S/PDIF • Integrated I2S serial port for up to 5.1 channel audio output port is also integrated for transmitting digital audio output and stereo input. streams. • Direct interface for IDE devices and flash memory cards A 16-bit host interface present in the ES6425 connects to including CF, MS, MS Pro, SD, xD, MMC, and SM. many different storage solutions including Compact • DRAM memory controller with interface to 8-bit or 16-bit Flash, Smart Media, xD-Picture Card, and IDE hard SDRAM for up to 16 MB of memory. drives. Similarly, a serial interface is built-in to interface to SD, xD, MultiMediaCard, and Memory Stick • 16-bit SRAM interface for connecting to boot EPROM or devices. flash memory. The ES6425 is available in an industry-standard 208-pin • Lead-free leads using 98%-Sn/2%-Cu or 98%-Sn/2%-Bi. Plastic Quad Flat Pack (PQFP) device package. ESS Technology, Inc. SAM0529-091305 1
  • 2. 2 LCS0#/PIXOUT_CLK HA2/AUX4[4] IOW#/AUX2 VSS LA3 LA2 LA1 LA0 CAMIN1 CAMIN0 VEE VSS LWRHL# LWRLL# LD15 LD14 LD13 LD12 VEE VSS LD11 LD10 LD9 LD8 LD7 LD6 LD5 VSS VEE LD4 LD3 LD2 LD1 LD0 VSS LCS3# LCS2# LCS1# VSS LOE# AUX7 AUX6 AUX5 AUX4 IORD#/AUX3 VEE VSS I2C_CLK/AUX1 I2CDATA/AUX0 VEE VEE VCC 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 VEE 1 156 VSS LA4 2 155 HA1/AUX4[3] LA5 3 154 HA0/AUX4[2] SAM0529-091305 LA6 4 153 HCS3FX3#/AUX3[6] LA7 5 152 HCS1FX#/AUX3[7] LA8 6 151 HIOCS16#/AUX3[4] LA9 7 150 HRD#/AUX4[6] ES6425 PINOUT DIAGRAM VSS 8 149 HWR#/AUX4[5] VCC 9 148 VEE LA10 10 147 VSS LA11 11 146 HIORDY/AUX3[3] LA12 12 145 HRST#/AUX3[5] LA13 13 HIRQ/AUX4[7] 144 pound symbol (#) denotes an active-low signal. LA14 14 143 HRRQ#/AUX4[0]/CAMIN2 LA15 15 142 HWRQ#/AUX4[1] LA16 16 141 HD15/AUX2[7]/IR VSS 17 140 HD14/AUX2[6] VEE 18 139 VCC LA17 19 138 VSS LA18 20 HD13/AUX2[5] 137 LA19 21 HD12/AUX2[4] 136 LA20 22 135 HD11/AUX2[3] LA21 23 134 HD10/AUX2[2] The device pinout for the ES6425 is shown in Figure 1. The RESET# 24 HD9/AUX2[1] 133 TDMDX/RSEL 25 HD8/AUX2[0]/VFD_CLK 132 VSS 26 HD7/AUX1[7]/VFD_DIN 131 VEE 27 VEE 130 TDMDR 28 VSS 129 TDMCLK 29 HD6/AUX1[6]/VFD_DOUT 128 TDMFS 30 HD5/AUX1[5] 127 TDMTSC# 31 ES6425 HD4/AUX1[4] 126 TWS/SEL_PLL2 32 HD3/AUX1[3] 125 TSD0/SEL_PLL0 33 HD2/AUX1[2] 124 VSS 34 HD1/AUX1[1] 123 VCC Figure 1 ES6425 Device Pinout 35 HD0/AUX1[0] 122 TSD1/SEL_PLL1 36 VCC 121 TSD2 37 VSS 120 Note: (*) MPEG-4 Advanced Simple Profile without hardware Q-PEL and Global Motion Compensation (GMC). NC 38 HSYNC#/AUX3[0]/CAMIN7 119 MCLK 39 VSYNC#/AUX3[1]/CAMIN6 118 TBCK 40 PCLKQSCN/AUX3[2]/CAMIN5 117 SPDIF/SEL_PLL3 41 PCLK2XSCN/CAMIN4 116 NC 42 YUV7/PIXOUT7 115 VSS 43 YUV6/VDAC/PIXOUT6 114 VCC 44 YUV5/YDAC/PIXOUT5 113 RSD 45 ADVSS 112 RWS 46 ADVEE 111 RBCK 47 YUV4/RSET/PIXOUT4 110 CAMIN3 48 YUV3/COMP/PIXOUT3 109 XIN 49 YUV2/CDAC/PIXOUT2 108 XOUT 50 YUV1/VREF/PIXOUT1 107 AVEE 51 YUV0/UDAC/PIXOUT0 106 AVSS 52 DCLK 105 62 55 56 57 58 59 60 61 65 68 53 54 63 64 66 67 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 VEE VSS VSS VEE VEE VSS VSS VSS VEE VSS VEE VSS VEE VCC DQM DB11 DB10 DB12 DB13 DB14 DB15 DMA0 DMA1 DMA2 DMA3 DMA4 DMA5 DMA6 DMA7 DMA8 DMA9 DSCK DWE# DCS1# DCS0# DMA11 DMA10 DCAS# DRAS# DMBS0 DMBS1 DOE#/DSCK_EN ESS Technology, Inc. ES6425 PRODUCT BRIEF ES6425 PINOUT DIAGRAM
  • 3. ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION ES6425 PIN DESCRIPTION Table 1 lists the pin descriptions for the ES6425. The pound symbol (#) denotes an active-low signal. Table 1 ES6425 Pin Description Name Pin Numbers I/O Definition 1,18, 27, 59, 68, 75, 92, 99, 104, 130, VEE P I/O power supply. 148, 157, 159, 164, 183, 193, 201 2-7, 10-16, 19-23, LA[21:0] O RISC port address bus. 204-207 8, 17, 26, 34, 43, 60, 67, 76, 84, 91, 98, 103, 120, 129, VSS G Ground. 138, 147, 156, 163, 171, 177, 184, 192, 200, 208 9, 35, 44, 83, 121, VCC I Core power supply. 139, 172 RESET# 24 I Reset input (active-low); (5V tolerant input). TDMDX O TDM transmit data. I LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-kΩ resistor; read during reset. 25 RSEL Selection RSEL 0 16-bit ROM 1 8-bit ROM TDMDR 28 I TDM receive data; (5V tolerant input). TDMCLK 29 I TDM clock; (5V tolerant input). TDMFS 30 I TDM frame sync; (5V tolerant input). TDMTSC# 31 O TDM output enable (active-low). TWS O Audio transmit frame sync. System and DSCK output clock frequency selection is made at the rising edge of RESET#. The matrix below lists the available clock frequencies and their respective PLL bit settings. Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset. SEL_PLL2 SEL_PLL1 SEL_PLL0 Clock Type 0 0 0 DCLK x 4.5 0 0 1 DCLK x 5.0 32 SEL_PLL2 I 0 1 0 Bypass mode 0 1 1 DCLK x 4.0 1 0 0 DCLK x 4.25 1 0 1 DCLK x 4.75 1 1 0 DCLK x 5.5 1 1 1 DCLK x 6.0 TSD0 O Audio transmit serial data output 0. 33 SEL_PLL0 I Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset. ESS Technology, Inc. SAM0529-091305 3
  • 4. ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION Table 1 ES6425 Pin Description (Continued) Name Pin Numbers I/O Definition TSD1 O Audio transmit serial data output 1. 36 SEL_PLL1 I Pull up to VCC via 4.7-kΩ resistor for proper operation; read during reset. TSD2 37 O Audio transmit serial data output 2. This pin must be pulled down to VSS via a 4.7-kΩ resistor for proper operation. MCLK 39 I/O Audio master clock for audio DAC. TBCK 40 I/O Audio transmit bit clock. TBCK is an input during reset and subsequently is programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4). SPDIF O S/PDIF output. 41 SEL_PLL3 I Pull down to ground via 4.7-kΩ resistor for proper operation; read during reset. NC 38, 42 — No connect. RSD 45 I Audio receive serial data; (5V tolerant input). RWS 46 I Audio receive frame sync; (5V tolerant input). RBCK 47 I Audio receive bit clock; (5V tolerant input). CAMIN3 48 I Camera and YUV input 3. XIN 49 I 27-MHz crystal input. XOUT 50 O 27-MHz crystal output. AVEE 51 P Analog power for PLL. AVSS 52 G Analog ground for PLL. DMA[11:0] 53-58, 61-66 O DRAM address bus. DCAS# 69 O DRAM column address strobe (active-low). DOE# O DRAM output enable (active-low). 70 DSCK_EN O DRAM clock enable. DWE# 71 O DRAM write enable (active-low). DRAS# 72 O DRAM row address strobe (active-low). DMBS0 73 O SDRAM bank select 0. DMBS1 74 O SDRAM bank select 1. DB[15:0] 77-82, 85-90, 93-96 I/O DRAM data bus. DCS[1:0]# 97,100 O SDRAM chip select (active-low). DQM 101 O Data input/output mask. DSCK 102 O Output clock to SDRAM. DCLK 105 I Clock input to PLL; (5V tolerant input). 4 SAM0529-091305 ESS Technology, Inc.
  • 5. ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION Table 1 ES6425 Pin Description (Continued) Name Pin Numbers I/O Definition O Video DAC output: DAC V DAC Y DAC C DAC U Value (pin 114) (pin 113) (pin 108) (pin 106) 0 CVBS1 Y N/A C 1 CVBS1 Y CVBS2 C 2 N/A Y N/A C 3 CVBS1 N/A CVBS2 N/A 4 CVBS1 N/A N/A N/A 5 CVBS1 Y Pr Pb 6 N/A Y Pr Pb 7 SYNC G R B 106 UDAC 8 CHROMA Y Pr Pb 9 CVBS1 G R B 10 CVBS1 G B R 11 SYNC G B R 12 N/A Y Pb Pr 13 CVBS1 Y Pb Pr Y: Luma component for YUV and Y/C processing. C: Chrominance signal for Y/C processing. U: Chrominance component signal for YUV mode. V: Chrominance component signal for YUV mode. YUV0 O YUV pixel 0 output data. PIXOUT0 O CCIR656 output pixel 0. VREF I Internal voltage reference to DAC. Bypass to ground with 0.1-µF capacitor. YUV1 107 O YUV pixel 1 output data. PIXOUT1 O CCIR656 output pixel 1. CDAC O Chrominance signal for Y/C processing display. YUV2 108 O YUV pixel 2 output data. PIXOUT2 O CCIR656 output pixel 2. COMP I Compensation input. Bypass to ADVEE with 0.1-µF capacitor. YUV3 109 O YUV pixel 3 output data. PIXOUT3 O CCIR656 output pixel 3. RSET I DAC current adjustment resistor input. YUV4 110 O YUV pixel 4 output data. PIXOUT4 O CCIR656 output pixel 4. ADVEE 111 P Analog power. ADVSS 112 G Analog ground for video DAC. YDAC O Luma component for Y/C processing display. YUV5 113 O YUV pixel 5 output data. PIXOUT5 O CCIR656 output pixel 5. VDAC O Video DAC output. Refer to description and matrix for UDAC pin 106. YUV6 114 O YUV pixel 6 output data. PIXOUT6 O CCIR656 output pixel 6. ESS Technology, Inc. SAM0529-091305 5
  • 6. ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION Table 1 ES6425 Pin Description (Continued) Name Pin Numbers I/O Definition YUV7 O YUV pixel 7 output data. 115 PIXOUT7 O CCIR656 output pixel 7. PCLK2XSCN I/O 27-MHz video pixel clock. 116 CAMIN4 I Camera and YUV input 4. PCLKQSCN O 13.5-MHz video output pixel clock. AUX3[2] 117 I/O Aux3 data I/O; (5V tolerant input). CAMIN5 I Camera and YUV input 5 VSYNC# I/O Vertical sync (active-low); (5V tolerant input). AUX3[1] 118 I/O Aux3 data I/O; (5V tolerant input). CAMIN6 I Camera and YUV input 6. HSYNC# I/O Horizontal sync (active-low); (5V tolerant input). AUX3[0] 119 I/O Aux3 data I/O; (5V tolerant input). CAMIN7 I Camera and YUV input 7. HD[5:0] I/O Host data bus; (5V tolerant input). 122-127 AUX1[5:0] I/O Aux1 data I/O; (5V tolerant input). HD6 I/O Host data bus; (5V tolerant input). AUX1[6] 128 I/O Aux1 data I/O; (5V tolerant input). VFD_DOUT O VFD data output. HD7 I/O Host data bus; (5V tolerant input). AUX1[7] 131 I/O Aux1 data I/O; (5V tolerant input). VFD_DIN I VFD data input. HD8 I/O Host data bus; (5V tolerant input). AUX2[0] 132 I/O Aux2 data I/O; (5V tolerant input). VFD_CLK I VFD clock. HD9 I/O Host data bus; (5V tolerant input). 133 AUX2[1] I/O Aux2 data I/O; (5V tolerant input). HD10 I/O Host data bus; (5V tolerant input). 134 AUX2[2] I/O Aux2 data I/O; (5V tolerant input). HD11 I/O Host data bus; (5V tolerant input). 135 AUX2[3] I/O Aux2 data I/O; (5V tolerant input). HD12 I/O Host data bus; (5V tolerant input). 136 AUX2[4] I/O Aux2 data I/O; (5V tolerant input). HD13 I/O Host data bus; (5V tolerant input). 137 AUX2[5] I/O Aux2 data I/O; (5V tolerant input). HD14 I/O Host data bus; (5V tolerant input). 140 AUX2[6] I/O Aux2 data I/O; (5V tolerant input). HD15 I/O Host data bus; (5V tolerant input). AUX2[7] 141 I/O Aux2 data I/O 7; (5V tolerant input). IR I IR remote control; (5V tolerant input). HWRQ# O Host write request (active-low). 142 AUX4[1] I/O Aux4 data I/O 1; (5V tolerant input). 6 SAM0529-091305 ESS Technology, Inc.
  • 7. ES6425 PRODUCT BRIEF ES6425 PIN DESCRIPTION Table 1 ES6425 Pin Description (Continued) Name Pin Numbers I/O Definition HRRQ# O Host read request (active-low). AUX4[0] 143 I/O Aux4 data I/O 0; (5V tolerant input). CAMIN2 I Camera and YUV input 2. HIRQ O Host interrupt. 144 AUX4[7] I/O Aux4 data I/O 7; (5V tolerant input). HRST# O Host reset (active-low). 145 AUX3[5] I/O Aux3 data I/O 5; (5V tolerant input). HIORDY I Host I/O ready. 146 AUX3[3] I/O Aux3 data I/O 3; (5V tolerant input). HWR# O Host write (active-low). 149 AUX4[5] I/O Aux4 data I/O 5; (5V tolerant input). HRD# O Host read (active-low). 150 AUX4[6] I/O Aux4 data I/O 6; (5V tolerant input). HIOCS16# I Device 16 bit data transfer (active-low). AUX3[4] 151 I/O Aux3 data I/O 4; (5V tolerant input). CAMCLK I Camera and YUV port pixel clock. HCS1FX# O Host select 1 (active-low). 152 AUX3[7] I/O Aux3 data I/O 7; (5V tolerant input). HCS3FX# O Host select 3 (active-low). 153 AUX3[6] I/O Aux3 data I/O 6; (5V tolerant input). HA[2:0] I/O Host address bus. 154, 155, 158 AUX4[4:2] I/O Aux4 data I/Os 2, 3, and 4; (5V tolerant input). AUX0 I/O Auxiliary port 0 (open collector); (5V tolerant input). 160 I2CDATA I/O I2C data I/O; (5V tolerant input). AUX1 I/O Auxiliary port 1 (open collector); (5V tolerant input). 161 I2C_CLK I/O I2C clock I/O; (5V tolerant input). IOW# O I/O write strobe (LCS1) (active-low). 162 AUX2 I/O Auxiliary port 2; (5V tolerant input). IOR# O I/O read strobe (LCS1) (active-low). 165 AUX3 I/O Auxiliary port 3; (5V tolerant input). AUX4-7 166-169 I/O Auxiliary ports 4-7; (5V tolerant input). LOE# 170 O RISC port output enable (active-low). LCS0# O RISC port chip select 0 (active-low). 173 PIXOUT_CLK O CCIR656 output pixel clock. LCS[3:1]# 174-176 O RISC port chip select [3:1] (active-low). 178-182, 185-191, LD[15:0] I/O RISC port data bus; (5V tolerant input). 194-197 LWRLL# 198 O RISC port low-byte write enable (active-low). LWRHL# 199 O RISC port high-byte write enable (active-low). CAMIN0 202 I Camera and YUV input 0. CAMIN1 203 I Camera and YUV input 1. ESS Technology, Inc. SAM0529-091305 7
  • 8. ES6425 PRODUCT BRIEF SYSTEM BLOCK DIAGRAM SYSTEM BLOCK DIAGRAM A sample system block diagram for the ES6425 board design is shown in Figure 2. Video ROM/Flash (1 MB) ADC Audio Audio SDRAM ES6425 Speakers DAC (4/16 MB) DMP2 S/PDIF A/V Receiver EEPROM IR Remote IDE HDD Memory Cards Figure 2 ES645 System Block Diagram ORDERING INFORMATION Part Number Description Package ES6425FF Digital Media Processor 2 with lead-free leads. 208-pin PQFP ES6425FDF Digital Media Processor 2 with Dolby Digital support and lead-free leads. 208-pin PQFP The letter F at the end of the part number identifies the package type PQFP. The second letter F at the end of the part number indicates lead-free leads with the device. No part of this publication may be reproduced, stored in a retrieval MPEG is the Moving Picture Experts Group of the ISO/IEC. References system, transmitted, or translated in any form or by any means, to MPEG in this document refer to the ISO/IEC JTC1 SC29 committee electronic, mechanical, manual, optical, or otherwise, without the prior draft ISO 11172 dated January 9, 1992. written permission of ESS Technology, Inc. Vibratto, SmartBright, SmartLogo, SmartColor, and Music Slideshow ESS Technology, Inc. makes no representations or warranties are trademarks of ESS Technology, Inc. ESS Technology, Inc. regarding the content of this document. Dolby is a trademark of Dolby Laboratories, Inc. All specifications are subject to change without prior notice. 48401 Fremont Blvd. Trusurround, Trusurround XT, SRS, and (o) symbol are trademarks of ESS Technology, Inc. assumes no responsibility for any errors SRS Labs., Inc. Fremont, CA 94538 contained herein. All other trademarks are trademarks of their respective companies and U.S. patents pending. are used for identification purposes only. Tel: (510) 492-1088 Fax: (510) 492-1898 8 http://www.esstech.com © 2005 ESS Technology, Inc. SAM0529-091305
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